1. Field of the Invention
The present invention relates to a fixed point signal processor, and more specifically to a fixed point signal processor having a high real-time processing capability.
2. Description of Related Art
Recent remarkably advanced LSI technology has elevated the processing speed and performance of a microprocessor, particularly a signal processor, which has an advanced audio or voice compression technology.
In order to realize a voice encoding processing having a high compression ratio, the signal processor has been required to have both a high arithmetic processing capability and a high arithmetic processing precision. In order to elevate the arithmetic processing precision, a bit width of input and output registers in the arithmetic processing must be sufficiently large.
On the other hand, a voice compression processing performed in the signal processor is generally based on a product-and-sum arithmetic operation in which two items of 16-bit data are multiplied and the result of multiplication is cumulatively summed.
Now, a fixed point arithmetic operation of "n"-bit data will be described with reference to FIG. 1. For example, "n"=16. As shown in FIG. 1, a pair of input data of "n" bits are supplied to a pair of inputs of a multiplication unit, and output data of the multiplication unit is "2n" bits. The width of a register for cumulating the output of the multiplication unit is on the order of "2n+.alpha." bits.
The ".alpha." bits are extended or extra bits for control of the product-and-sum arithmetic operation, for the purpose of holding an overflowed or underflowed condition of the product-and-sum arithmetic operation. In ordinary cases, the ".alpha." bits are on the order of 4 bits or 8 bits.
Incidentally, the most significant bit (MSB) of each of the "n"-bit input data and the "2n"-bit multiplication result data is indicative of a sign bit "S". The radix point is determined between the sign bit "S" and an adjacent bit that is at the right side of the sign bit. Therefore, the right side adjacent bit is indicative of "1/2".
Since the number of significant digits is "n" bits, an effective "n"-bit portion of the obtained arithmetic operation result is saved into a data memory, and the saved effective "n"-bit portion is used as an input of the multiplication unit, in order to maintain the arithmetic operation precision.
Because of the above, a conventional signal processor has been constituted as shown in FIG. 2.
In FIG. 2, an ALU (arithmetic and logic unit) 31 is configured to perform a fixed point product-and-sum arithmetic operation, a shift operation, and other general arithmetic and logic operations. A memory data bus 32 has an "n"-bit width and is exclusively used for a memory access, and a main data bus 33 is a main bus also having an "n"-bit width.
General registers 34 have an "2n+.alpha."-bit width, and are coupled to the ALU 31 for storing inputs and an output of the ALU 31. A selection circuit 35 is coupled between the general registers 34 and the memory and main data buses 32 and 33. When data on the memory data bus 32 or on the main data bus 33 is supplied to the general register 34, the selection circuit 35 extends the data of the "n"-bit width to the data of the "2n+.alpha."-bit width. On the other hand, when data on the general register 34 is supplied to the memory data bus 32 or the main data bus 33, the selection circuit 35 selects and outputs either the most significant "n" bits or the least significant "n" bits of the "2n+.alpha."-bit data.
A data memory 36 has an "n"-bit width, and is coupled to the memory data bus 32 and is used to save the arithmetic operation result in the general registers 34 through the memory data bus 32.
With the above mentioned arrangement, a processing called a "block floating" is ordinarily used in order to maintain a high arithmetic operation precision with a decreased amount of processing.
In this block floating processing, for a group of numerical data which has a bit width larger than the bit width of the dam memory and the inputs of the multiplication unit and which has correlation in a dynamic range between items of numerical data as can be typified by a voice signal, the group of numerical data are normalized in a common scale value (called a "block scale value" hereinafter), so that the arithmetic operation precision of the numerical data is maintained when the numerical data is saved to the memory or supplied to the input of the multiplication unit.
Referring to FIG. 3, there is shown a group of examples of fixed point data for which the block floating processing is performed. In FIG. 3, a group "a" composed of a plurality of items of numerical data having "2n+.alpha." bits in length are the data of the arithmetic operation result. As shown, these items of numerical data in the group "a" correlate to each other in a dynamic range to each other. More specifically, the items of numerical data in the group "a" correlate to the fixed point representation of the numerical data.
In FIG. 3, in order to save the most effective "n" bits to the memory or to supply the most effective "n" bits to the multiplication unit, an "n"-bit portion of a data group "b" having opposite ends confined by dotted lines is selected. In addition, 11 bits of "0" continue from the MSB bit (inclusive) adjacent to the extended bits ".alpha.". Of the continuous "0" bits, the position of the "0" bit adjacent to the dotted line indicates the block scale value. Namely, the block scale value is 11 in the shown example.
The MSB bit of each numerical data in the data group "b" is allocated as a sign bit for each numerical data in the data group "b". The radix point is determined between the sign bit of the numerical data in the data group "b" and a fight side bit adjacent to the sign bit.
Specifically, normalization of the numerical data by the above mentioned block scale value means to select from the dam group "a" the data group "b" confined by the dotted lines on the basis of the scale value.
Incidentally, in FIG. 3, the MSB "n" bits and the LSB "n" bits can be directly accessed in units of one word for example in the case of "n"=16. However, each data of 16 bits in the data group "b" bridging the MSB "n" bits and the LSB "n" bits cannot be directly extracted, but can be extracted after performing a bit shifting processing.
Therefore, in the case that in the conventional signal processor shown in FIG. 2, the above mentioned block floating processing is performed for "m" items of numerical data, the following processing is performed.
First, the following steps (1), (2) and (3) are repeated "m" times for obtaining "in" scale values required.
(1) The data of the "2n+.alpha."-bit width, which is the arithmetic operation result of the ALU 31, is outputted to the general registers 34 having the "2n+.alpha."-bit width; PA1 (2) A comparison processing is performed to search a maximum value of the data obtained in the step (1); and PA1 (3) The data of the "2n+.alpha."-bit width held in the general registers 34 in the step (1) is modified, by the selection circuit 35, to a 2-word data in the form of "n.times.2" bits, and saved to the data memory 36 of the "n"-bit width, while maintaining the arithmetic operation precision. PA1 (4) The block scale value for the "m" items of numerical data is derived from the maximum value obtained in the step (2). PA1 (6) The data held in the general register 34 in the step (5) is shifted in the ALU 31 in accordance with the block scale value obtained in the step (4); and PA1 (7) MSB "n" bits of the data shifted in the step (6) are written to the data memory 36 of the "n"-bit width through the selection circuit 35 as the "n"-bit data obtained by normalizing the "2n+.alpha."-bit data which is the arithmetic operation result in the step (1). PA1 an arithmetic operation means of "2n+.alpha."-bit width, receiving input data of "n" bits width, for performing a predetermined arithmetic operation including a fixed point product-and-sum operation and a shift operation, where "n" is a positive integer larger than "1" and is indicative of a bit width of input data, and ".alpha." is a positive integer indicative of a predetermined extended bit width; PA1 a fast memory means of "2n+.alpha."-bit width, for temporarily holding input and output data of the arithmetic operation means; PA1 a second memory means of "n"-bit width, for saving data of "n"-bit width, which is a portion of the data stored in the first memory means; PA1 a first selection means for extending the "n"-bit width data held in the second memory means to "2n+.alpha."-bit width to output the extended data to the first memory means, the first selection means selecting an "n"-bit portion composed of continuous "n" bits from the "2n+.alpha."-bit width data held in the first memory means, to output the selected "n"-bit portion to the second memory means in units of "n"-bit width; PA1 a third memory means receiving the "2n+.alpha."-bit width data held in the first memory means for saving a plurality of items of "2n+.alpha."-bit width data; PA1 a means for indicating a head position of continuous "n" bits in the "2n+.alpha."-bit width data held in the third memory means; and PA1 a second selection means for selecting, from the "2n+a"-bit width data held in the third memory means, the continuous "n" bits starting from the head position indicated by the indicating means, to output the selected continuous "n" bits to the first selection means. PA1 (A) The block floating processing is generally used in flag voice compression technology, and therefore, has general-purpose properties which are independent of the algorithm. PA1 (B) In a VSELP (vector sum excited linear prediction) which is a Japanese digital automobile telephone system, it is necessary to treat data of 2K words per frame, by the block floating processing. PA1 (3) The block floating processing can be realized by only data selection and transfer, and therefore, can be reduced or transformed into hardware having simple circuitry.
As a result, the "m" items of numerical data of the "2n+.alpha."-bit width, is saved in the data memory 36 in the form of "n.times.2" bits.
Next, the following steps (5), (6) and (7) are repeated "m" times for normalizing the "m" items of "2n+.alpha."-bit data and storing the normalized data in the data memory 36 so that the numerical data can be supplied to the multiplication unit while maintaining the arithmetic precision.
(5) The data saved in the data memory 36 in the form of "n.times.2" bits is read out through the selection circuit 35 to the general register 34 in the form of "2n+.alpha."-bit data;
Thus, the group of "2n+.alpha."-bit numerical data which is the result of the arithmetic operation processing in the step (1), is normalized to the "n" bits, and stored "m" items in the data memory 36.
With the above mentioned processing, in the case that the "2n+.alpha."-bit data, which is the result of the arithmetic operation processing, is used as an "n"-bit input data for multiplication, the arithmetic operation precision can be maintained by using the "n"-bit data normalized in the steps (5), (6) and (7).
Incidentally, each of the steps (5), (6) and (7) corresponds to one instruction in the signal processor.
Here, the real-time processing capability of the signal processor depends upon an operating frequency (instruction cycle time) of the processor, which is limited by LSI technology.
However, a recent voice encoding system having an extremely high compression ratio, demands both a high arithmetic operation processing capability and a high arithmetic operation precision. Accordingly, the amount of arithmetic operations required in the signal processor for performing a high efficiency voice compression encoding is tremendous.
The required compression ratio is apt to increase more and more in the future, and therefore, the required amount of arithmetic operation processing will correspondingly increase more and more. Thus, the real-time processing capability of the signal processor will gradually approach a load limit in view of a relation between the operating frequency and the amount of arithmetic operation processing.